1. Field of the Invention
The present invention relates to a method for manufacturing a power semiconductor device, and more particularly, to a method for manufacturing a trench-gate type power semiconductor device, which is simplified by using a smaller number of masks and exhibits improved characteristics.
2. Description of the Related Art
Trench-gate type power semiconductor devices are used in step motors, driving integrated circuits (ICs) of flat panel displays, or direct current to direct current (DC/DC) converters. Such trench-gate type power semiconductor devices have a high integration density and improved electrical characteristics, such as low on-resistance. However, in most cases, 5-6 masks are required to manufacture a trench-gate type power semiconductor device, and the manufacturing process is very complicated.
Due to the complicated manufacturing process, the characteristics of a device may deteriorate. For example, if an etching process, such as a reactive ion etching process, is performed to form a trench, the surface of a silicon substrate that is exposed by the trench is damaged. Next, if a gate oxide layer is formed on the damaged surface of the silicon substrate that is exposed by the trench, the state of the interface between the gate oxide layer and the surface of the silicon substrate deteriorates. In addition, spherical junctions are generated at each corner of the trench, and thus an electrical field is concentrated at the corners of the trench. Accordingly, the breakdown voltage of a device decreases, and thus the stability of the device also decreases.
To solve the above-described problems, it is an object of the present invention to provide a method for manufacturing a trench-gate type power semiconductor device which, by forming a sidewall oxide layer and using a self-alignment technique, requires a smaller number of masks and does not deteriorate the characteristics of a device.
Accordingly, to achieve the above object, there is provided a method for manufacturing a trench-gate type power semiconductor device. The method includes forming a drift region having a low concentration of a first conductivity type on a semiconductor substrate having a high concentration of the first conductivity type, forming an oxide layer on the drift region, forming a nitride layer pattern and a photoresist layer pattern that are sequentially stacked on the oxide layer, forming a body region of a second conductivity type in the drift region by implanting impurity ions of the second conductivity type using the nitride layer pattern and the photoresist layer pattern as an ion implantation mask, removing the photoresist layer pattern, forming a sidewall oxide layer at sidewalls of the nitride layer pattern, forming a trench perforating the body region by etching predetermined portions of the body region exposed by the nitride layer pattern and the sidewall oxide layer, partially exposing predetermined portions of the body region by removing the sidewall oxide layer, rounding the corners of the trench by performing a heat treatment in a hydrogen atmosphere, forming a gate oxide layer on the exposed portions of the body region and at the inner sidewalls of the trench, forming a gate conductive layer on the gate oxide layer to fill the trench, forming a source region having a high concentration of the first conductivity type along the upper edges of the trench in the body region by implanting impurity ions of the first conductivity type using the nitride layer pattern as an ion implantation mask, forming an upper oxide layer pattern to cover a portion of the source region and the gate conductive layer, removing the nitride layer pattern, forming a body contact region of the second conductivity type in a predetermined portion of the body region by implanting impurity ions of the second conductivity type using the upper oxide layer pattern as an ion implantation mask, forming a source electrode to be electrically connected to the body contact region and the source region, and forming a drain electrode to be electrically connected to the semiconductor substrate.
Preferably, the etching process used to form the trench is a reactive ion etching process.
Preferably, the heat treatment is performed in a hydrogen atmosphere at a temperature of 900-1000xc2x0 C.
Preferably, the upper oxide layer pattern is formed of an O3-TEOS oxide layer.
Preferably, forming the upper oxide layer pattern includes forming an upper oxide layer on the entire surface of the semiconductor substrate, and forming the upper oxide layer pattern by etching back the upper oxide layer to expose the top surface of the nitride layer pattern.
The method for manufacturing a trench-gate type power semiconductor device may further include performing a sacrificial oxidation process after forming the trench.